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T66H0001A
T66H0001A
FEATURES
! ! ! ! ! ! Number of LCD drive outputs : 240 Supply voltage for LCD drive : ( +10.0 to +42.0 V) Supply voltage for logic system : ( +2.5 to +5.5 V) Low power consumption Low output impedance Package : 269-pin TCP (Tape Carrier Package)
240 output LCD Segment/Common Driver IC
DESCRIPTION
The T66H0001A is a 240-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The T66H0001A is good both as a segment driver and a common driver, and it can create a low power consuming, high resolution LCD
Segment mode:
1. Shift clock frequency - 20 MHz (MAX.) : VDD = +5.0 0.5 V - 15 MHz (MAX.) : VDD = +3.0 to +4.5 V - 12 MHz (MAX.) : VDD = +2.5 to +3.0 V 2. Adopts a data bus system 3. 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin 4. Automatic transfer function of an enable signal 5. Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data 6. Line latch circuits are reset when /DISPOFF low active
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T66H0001A
Common mode:
- Shift clock frequency: 4 MHz (MAX.) - Built-in 240-bit bi-directional shift register (divisible into 120 bits x 2) - Available in single mode (240-bit shift register) or in dual mode (120-bit shift register x 2) a. Y1 # Y240 Single mode b. Y240 # Y1 Single mode c. Y1# Y120, Y121#Y240 Dual mode d. Y240 #Y121, Y120 # Y1 Dual mode The above 4 shift directions are pin selectable - Shift register circuits are reset when /DISPOFF low active
Part Number Examples
Part No. Pkg. Description T66H0001A-Y TCP Pitch 0.21mm, refer to Appendix T66H0001A COG Refer to Pads List
PIN CONNECTIONS
269-PIN TCP
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PIN NO.
1 to 240 241, 269 242, 268 243, 267 244, 266 245 246 247, 259 248 to 254 255 256 257 258 260 261 262 263, 264 265
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T66H0001A
PIN DESCRIPTION
SYMBOL
Y1-Y240 V0L, V0R V12L,V12R V43L,V43R V5L,V5R VDD S/C EIO2, EIO1 DI0-DI6 DI7 XCK /DISPOFF LP FR L/R MD NC VSS
I/O
O I I/O I I I I I I I I I -
DESCRIPTION
LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for logic system (+2.5V to +5.5V) Segment mode/common mode selection Input/output for chip selection at segment mode/ Shift data input/output for shift register at common mode Display data input at segment mode Display data input at segment mode/Dual mode data input at common mode Clock input for taking display data at segment mode Control input for output of non-select level Latch pules input for display data at segment mode Shift clock input for shift register at common mode AC-converting signal input for LCD drive waveform Input for selecting the reading direction of display data at segment mode/Input for selecting the shift direction of shift register at common mode Mode selection input Not Connection Ground(0V)
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T66H0001A
INPUT/OUTPUT CIRCUITS
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T66H0001A
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T66H0001A
BLOCK DIAGRAM
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T66H0001A
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
Active Control
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip. Following and LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit, after that they are put on the internal data 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. In case of segment mode, latches the data on the data bus. The latch state of each LCD rive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. In case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. The logic voltage signal is level-shifted to the LCD drive voltage level, and in output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels (V0, V12, V43, or V5) based on the S/C, FR and /DISPOFF signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are rest and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip in non-selected. In case of common mode, controls the direction of data shift.
SP Conversion & Data Control
Data Latch Control
Data Latch Line Latch/ Shift Register Level Shifter 4-Level driver
Control Logic
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T66H0001A
FUNCTIONAL DESCRIPTION Pin Functions
(Segment mode) SYMBOL
VDD Vss V0L , V0R V12L , V12R V43L , V43R V5L , V5R
FUNCTION
DI7 , DI0
XCK LP
L/R
/DISPOFF
FR
Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage * Normally use the bias voltages set by a resistor divider. * Ensure that voltages are set such that Vss V5 < V43 < V12 < V0. * ViL and ViR ( i= 0 , 12 , 43 , 5) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. Input pins for display data * In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. Connect DI7-DI4 to Vss or VDD. * In 8-bit parallel input mode, input data into the 8 pins, DI7- DI0. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data * Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data * When set to Vss level "L", data is read sequentially from Y240 to Y1. * When set to VDD level "H", data is read sequentially from Y1 to Y240. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * When set to Vss level "L", the LCD drive output pins (Y1-Y240) are set to level V5. * When set to "L" ,the contents of the line latch are reset , but the display data are read in the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * Normally it inputs a frame inversion signal. * The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
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MD S/C
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FUNCTION
T66H0001A
SYMBOL
EIO1 , EIO2
Y1-Y240
Mode selection pin * When set to Vss level "L" , 8 bit parallel input mode is set. * When set to VDD level "H" , 4 bit parallel input mode is set. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Segment mode/common mode selection pin * When set to VDD level "H" , segment mode is set. Input/output pins for chip selection * When L/R input is at Vss level "L" , EIO1 is set for output , and EIO2 is set for input. * When L/R input is at VDD level "H" , EIO1 is set for input , and EIO2 is set for output. * During output , set to "H" while LP*/XCK is "H" and after 240 bits of data have been read , set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H". * During input , the chip is selected while EI is set to "L" after the LP signal is input. The chip is non-selected after 240 bits of data have been read. LCD drive output pins * Corresponding directly to each bit of the data latch , one level (V0 , V12 , V43 , or V5) is selected and output. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
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VDD Vss V0L , V0R V12L , V12R V43L , V43R V5L , V5R
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T66H0001A
Common mode:
SYMBOL FUNCTION
Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage * Normally use the bias voltages set by a resistor divider. * Ensure that voltages are set such that Vss V5 < V43 < V12 < V0. * ViL and ViR ( i = 0 , 12 , 43 , 5) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register * Output pin when L/R is at Vss level "L" , input pin when L/R is at VDD level "H". * When L/R = H, EIO1 is used as input pin, it will be pulled down. * When L/R = L, EIO1 is used as output pin, it won't be pulled down. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Shift data input/output pin for bi-directional shift register * Input pin when L/R is at Vss level "L" , output pin when L/R is at VDD level "H". * When L/R = L, EIO2 is used as input pin, it will be pulled down. * When L/R = H, EIO2 is used as output pin, it won't be pulled down. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Latch pulse input pin for display data * Data is latched at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register * Data is shifted from Y240 to Y1 when set to Vss level "L" , and data is shifted from Y1 to Y240 when set to VDD level "H". * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * When set to Vss level "L", the LCD drive output pins (Y1-Y240) are set to level V5. * When set to "L", the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled , the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform * The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. * Normally it inputs a frame inversion signal. * The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
EIO1
EIO2
LP
L/R
/DISPOFF
FR
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FUNCTION
T66H0001A
SYMBOL
DI7
S/C DI6-DI0 XCK Y1-Y240
Mode selection pin * When set to Vss level "L" , single operation is selected ; when set to VDD level "H" , dual mode operation is selected. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Dual mode data input pin * According to the data shift direction of the data shift register , data can be input starting from the 121st bit. * When the chip is used in dual mode, DI7 will be pulled down. * When the chip is used in single mode, DI7 won't be pulled down. * Refer to " RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Segment mode/common mode selection pin * When set to Vss level "L, common mode is set. Not used * Connect DI6-DI0 to Vss or VDD, avoiding floating. Not used * XCK is pulled down in common mode, so connect to Vss or open. LCD drive output pins * Corresponding directly to each bit of the data latch , one level (V0 , V12 , V43 , or V5) is selected and output. * Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
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FR L L H H X
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T66H0001A
Functional Operations
TRUTH TABLE
(Segment Mode)
Latch Data L H L H X /DISPOFF H H H H L LCD Drive Output Voltage Level (Y1-Y240) V43 V5 V12 V0 V5
(Common Mode)
R L L H H X Latch Data L H L H X /DISPOFF H H H H L LCD Drive Output Voltage Level (Y1-Y240) V43 V0 V12 V5 V5
NOTES : * Vss <= V5 < V43 < V12 < V0, L: Vss (0 V), H: VDD (+2.5 to +5.5 V) , X : Don't care * "Don't care" should be fixed to "H" or "L", avoiding floating.
There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin.
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MD
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T66H0001A
RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS
(Segment Mode) (a) 4-bit Parallel Input Mode L/R EIO1 EIO2 DATA NUMBER OF CLOCKS IINPU 60 Clock 59 Clock 58 Clock ... 3 Clock 2 Clock 1 Clock T DI0 H L Output Input DI1 DI2 DI3 DI0 H H Input Output DI1 DI2 DI3 Y1 Y2 Y3 Y4 Y240 Y239 Y238 Y237 Y5 Y6 Y7 Y8 Y236 Y235 Y234 Y233 Y9 Y10 Y11 Y12 Y232 Y231 Y230 Y229
... ... ... ... ... ... ... ...
Y229 Y230 Y231 Y232 Y12 Y11 Y10 Y9
Y233 Y234 Y235 Y236 Y8 Y7 Y6 Y5
Y237 Y238 Y239 Y240 Y4 Y3 Y2 Y1
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T66H0001A
(b) 8 bit Parallel input Mode L/R EIO1 EIO2 DATA NUMBER OF CLOCKS IINPU 30 Clock 29 Clock 28 Clock ... 3 Clock 2 Clock 1 Clock T DI0 DI1 DI2 L L Output Input DI3 DI4 DI5 DI6 DI7 DI0 DI1 DI2 L H Input Output DI3 DI4 DI5 DI6 DI7 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17
Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9
Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
(Common Mode) MD L (Single) H (Dual) L/R L H L H Data Transfer Direction Y240 Y1 Y240 Y1 Y240 Y121 Y1 Y120 Y1 Y120 Y121 Y240 EIO1 Output Input Output Input EIO2 Input Output Input Output DI7 X X Input Input
NOTES : * L : Vss (0 V ) , H : VDD (+2.5 to +5.5 V) , X : Don't care * "Don't care" should be fixed to "H" or "L" , avoiding floating.
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T66H0001A
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS
(a) When L/R = "L"
(b) When L/R = "H"
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T66H0001A
CONNECTION EXAMPLES FOR PLURAL COMMON DRIVERS
(a) Single Mode (L/R = "L")
(b) Single Mode (L/R = "H")
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T66H0001A
(c) Dual Mode (L/R = "L")
(d) Dual Mode (L/R = "H")
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T66H0001A
PRECAUTIONS
Precautions when connecting or disconnecting the power supply
This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. * When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power , disconnect the logic system power after disconnecting the LCD drive power. * It is advisable to connect the serial resister (50 to 100 ) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resister in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecurity. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power , set the LCD drive output pins to level V5 on /DISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here.
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T66H0001A
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage(1) SYMBOL APPLICABLE PINS VDD VDD V0 V0L,V0R V12 V43 V5 Input voltage Storage temperature VI Tstg V12L, V12R V43L, V43R V5L, V5R DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF, TEST1, TEST2 RATING -0.3 to +7.0 -0.3 to +42.0 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to VDD + 0.3 -45 to +125 UNIT V V V V V V C 1,2 NOTE
Supply voltage(2)
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to Vss (0V).
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage(1) Supply voltage(2) Operating temperature AYMBOL APPLICABLE PINS MIN. VDD VDD +2.5 V0 V0L,V0R +10.0 TOPR -20 TYP. MAX. UNIT NOTE +5.5 V 1,2 +45.0 V +85 C
NOTES :
1. The applicable voltage on any pin with respect to Vss (0V). 2. Ensure that voltage are set such that Vss <= V5 < V43 < V12 < V0.
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T66H0001A
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Segment Mode) C)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current SYMBOL VIL VIH VOL VOH ILIL ILIH IOL = +0.4mA IOH = -0.4mA VI = Vss VI = VDD Vo=40V |*VON| =0.5V Vo=30V Vo=20V Standby current Supply current(1) (Non-selection) Supply current(2) (Selection) Supply current(3) ISTB IDD1 IDD2 IO VSS VDD VDD V0L,V0R CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE 0.2VDD V DI7-DI0, XCK, LP, L/R, FR, MD, S/C, V 0.8VDD EIO1, EIO2, /DISPOFF +0.4 V EIO1, EIO2 VDD-0.4 V DI7-DI0, XCK, LP, -10.0 uA L/R, FR, MD, S/C, +10.0 uA EIO1, EIO2, /DISPOFF 1.0 Y1 - Y240 1.5 2.0 1.5 2.0 2.5 50.0 5.0 5.0 700 uA mA mA uA 1 2 3 4 K
(VSS = V5 = 0V, VDD = +2.5 to +5.5V, V0 = +10.0 to +42.0V, TOPR = -20 to +85
Output resistance
RON
NOTES : 1. VDD = +5.0V, V0 = +42.0 V, VI = Vss. 2. VDD = +5.0V, V0 = +42.0 V,fXCK = 20 MHz, non-load, EI = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0V, V0 = +42.0 V,fXCK = 20 MHz, non-load, EI = Vss. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +5.0V, V0 = +42.0 V,fXCK = 20 MHz, fLP = 41.6 kHz, fFR = 80 Hz, non-load. The input data is turned over by data taking clock (4-bit parallel input mode).
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T66H0001A
(Vss = V5 = 0V, VDD = +2.5 to +5.5V, V0 = +10.0 to +42.0V, TOPR = -20 to +85 C)
SYMBOL VIL VIH VOL VOH ILIL IOL = +0.4mA IOH = -0.4mA VI = Vss VI = VDD VI = VDD Vo=40V |*VON| =0.5V Vo=30V Vo=20V CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE 0.2VDD V DI7-DI0, XCK, LP, L/R, FR, MD, S/C, V 0.8VDD EIO1, EIO2, /DISPOFF +0.4 V EIO1, EIO2 VDD-0.4 V DI7-DI0, XCK, LP, -10.0 uA L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF DI6-DI0, LP, L/R, FR, +10.0 uA MD, S/C, /DISPOFF DI7, XCK, EIO1, EIO2 100.0 uA 1.0 Y1 - Y240 1.5 2.0 Vss VDD V0L,V0R 1.5 2.0 2.5 50.0 120.0 200 uA uA uA 1 2 2 K
(Common Mode)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current
ILIH Input pull-down current IPD
Output resistance
RON
Standby current Supply current(1) Supply current(2)
ISTB IDD Io
NOTES : 1.VDD = +5.0V, V0 = +42.0 V, VI = Vss. 2.VDD = +5.0V, V0 = +42.0 V,fXCK = 20 MHz, fLP = 41.6 kHz, fFR = 80 Hz, 1/480 duty operation, no-load.
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AC Characteristics
(Segment Mode 1) (Vss = V5 = 0V, VDD = +5.0 0.5V, V0 = +10.0 to +42.0V, TOPR = -20 to +85 C)
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL twck twckh twckl tDS tDH twLPH tLD tSL tLS tLH ts tR tF tSD tWDL tD tPD1,tPD2 tPD3 CL= 15 pF CL= 15 pF CL= 15 pF CONDITIONS tR,tF 10 ns MIN. 50 15 15 10 12 15 0 30 25 25 10 TYP. MAX. UNIT NOTE ns 1 ns ns ns ns ns ns ns ns ns ns 50 ns 2 50 ns 2 ns us 30 1.2 1.2 ns us us
100 1.2
NOTES :
1. Takes the cascade connection into consideration 2. (twck - twckH - twckL )/2 is maximum in the case of high speed operation.
(Segment Mode 2) (Vss = V5 = 0V, VDD = +3.0 to +4.5V, V0 = +10.0 to +42.0V, TOPR = -20 to +85 C)
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL twck twckh twckl tDS tDH twLPH tLD tSL tLS tLH ts tR tF tSD tWDL tD tPD1,tPD2 tPD3 CL= 15 pF CL= 15 pF CL= 15 pF CONDITIONS tR,tF 10 ns MIN. 66 23 23 15 23 30 0 50 30 30 15 TYP. MAX. UNIT NOTE ns 1 ns ns ns ns ns ns ns ns ns ns 50 ns 2 50 ns 2 ns us 41 1.2 1.2 ns us us
100 1.2
NOTES :
1. 2. Takes the cascade connection into consideration (twck - twckH - twckL )/2 is maximum in the case of high speed operation.
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SYMBOL CONDITIONS tR,tF 10 ns MIN. 82 28 28 20 23 30 0 65 30 30 15
T66H0001A
TYP. MAX. UNIT NOTE ns 1 ns ns ns ns ns ns ns ns ns ns 50 ns 2 50 ns 2 ns us 57 ns 1.2 us 1.2 us
(Segment Mode 3) (Vss = V5 = 0V, VDD = +2.5 to +3.0V, V0 = +10.0 to +42.0V, TOPR = -20 to +85 C)
PARAMETER Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3)
twck twckh twckl tDS tDH twLPH
tLD tSL tLS tLH ts tR tF tSD tWDL tD tPD1,tPD2 tPD3
100 1.2 CL= 15 pF CL= 15 pF CL= 15 pF
NOTES :
1. 2. Takes the cascade connection into consideration (twck - twckH - twckL )/2 is maximum in the case of high speed operation.
TM Technology Inc. reserves the right P. 23 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
T66H0001A
Timing Chart of Segment Mode
TM Technology Inc. reserves the right P. 24 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
T66H0001A
(Common Mode ) (Vss = V5 = 0V, VDD = +2.5 to +5.5V, V0 = +10.0 to +42.0V, TOPR = -20 to +85 C) PARAMETER Shift clock period Shift clock "H" pulse width Data setup time Data hold time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL twck twckH tSU tH tR tF tSD tWDL tDL tPD1,tPD2 tPD3 100 1.2 CL= 15 pF CL= 15 pF CL= 15 pF 200 1.2 1.2 CONDITIONS tR,tF 10 ns VDD = +5.00.5V VDD = +2.5 to+4.5V MIN. 250 15 30 30 50 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns us ns us us
TM Technology Inc. reserves the right P. 25 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
T66H0001A
Timing Chart of Common Mode
TM Technology Inc. reserves the right P. 26 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
T66H0001A
Timing Chart Of 4-Device Cascade Connection Of Segment Drivers
TM Technology Inc. reserves the right P. 27 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
T66H0001A
SYSTEM CONFIGURATION EXAMPLE
TM Technology Inc. reserves the right P. 28 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
D
TE CH
T66H0001A
Pads List
D PAD240 PAD1 D T66H 0001A D D D D PAD241 D D D PAD295
D
D
"D" means dummy pads which are floating inside the chip. PAD SIZE : OUTPAD = 55x72(Pad 1 to Pad 240) INPAD = 70x72(Pad 241 to Pad 295) DUMMY = 70x80 OPEN WINDOW : OUTPAD = 29x46 INPAD = 44x46 DUMMY = 44x54 BUMP SIZE : OUTPAD = 43x60 INPAD = 54x56 DUMMY = 54x64 BUMP HEIGHT = 18 DIE SIZE = 14900 X 1070 (WITHOUT SCRIBE LINE) SCRIBE LINE = 80 UNIT = um
TM Technology Inc. reserves the right P. 29 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
X 7185.95 7125.95 7065.95 7005.95 6945.95 6885.95 6825.95 6765.95 6705.95 6645.95 6585.95 6525.95 6465.95 6405.95 6345.95 6285.95 6225.95 6165.95 6105.95 6045.95 5985.95 5925.95 5865.95 5805.95 5745.95 5685.95 5625.95 5565.95 5505.95 5445.95 5385.95 5325.95 5265.95 5205.95 5145.95 5085.95 5025.95 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 Pad No. Pin Name 38 Y38 39 Y39 40 Y40 41 Y41 42 Y42 43 Y43 44 Y44 45 Y45 46 Y46 47 Y47 48 Y48 49 Y49 50 Y50 51 Y51 52 Y52 53 Y53 54 Y54 55 Y55 56 Y56 57 Y57 58 Y58 59 Y59 60 Y60 61 Y61 62 Y62 63 Y63 64 Y64 65 Y65 66 Y66 67 Y67 68 Y68 69 Y69 70 Y70 71 Y71 72 Y72 73 Y73 74 Y74
T66H0001A
X 4965.95 4905.95 4845.95 4785.95 4725.95 4665.95 4605.95 4545.95 4485.95 4425.95 4365.95 4305.95 4245.95 4185.95 4125.95 4065.95 4005.95 3945.95 3885.95 3825.95 3765.95 3705.95 3645.95 3585.95 3525.95 3465.95 3405.95 3345.95 3285.95 3225.95 3165.95 3105.95 3045.95 2985.95 2925.95 2865.95 2805.95 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4
Pad No. Pin Name 1 Y1 2 Y2 3 Y3 4 Y4 5 Y5 6 Y6 7 Y7 8 Y8 9 Y9 10 Y10 11 Y11 12 Y12 13 Y13 14 Y14 15 Y15 16 Y16 17 Y17 18 Y18 19 Y19 20 Y20 21 Y21 22 Y22 23 Y23 24 Y24 25 Y25 26 Y26 27 Y27 28 Y28 29 Y29 30 Y30 31 Y31 32 Y32 33 Y33 34 Y34 35 Y35 36 Y36 37 Y37
TM Technology Inc. reserves the right P. 30 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
X 2745.95 2685.95 2625.95 2565.95 2505.95 2445.95 2385.95 2325.95 2265.95 2205.95 2145.95 2085.95 2025.95 1965.95 1905.95 1845.95 1785.95 1725.95 1665.95 1605.95 1545.95 1485.95 1425.95 1365.95 1305.95 1245.95 1185.95 1125.95 1065.95 1005.95 945.95 885.95 825.95 765.95 705.95 645.95 585.95 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 Pad No. Pin Name 112 Y112 113 Y113 114 Y114 115 Y115 116 Y116 117 Y117 118 Y118 119 Y119 120 Y120 121 Y121 122 Y122 123 Y123 124 Y124 125 Y125 126 Y126 127 Y127 128 Y128 129 Y129 130 Y130 131 Y131 132 Y132 133 Y133 134 Y134 135 Y135 136 Y136 137 Y137 138 Y138 139 Y139 140 Y140 141 Y141 142 Y142 143 Y143 144 Y144 145 Y145 146 Y146 147 Y147 148 Y148
T66H0001A
X 525.95 465.95 405.95 345.95 285.95 225.95 165.95 105.95 45.95 -46.25 -106.25 -166.25 -226.25 -286.25 -346.25 -406.25 -466.25 -526.25 -586.25 -646.25 -706.25 -766.25 -826.25 -886.25 -946.25 -1006.25 -1066.25 -1126.25 -1186.25 -1246.25 -1306.25 -1366.25 -1426.25 -1486.25 -1546.25 -1606.25 -1666.25 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4
Pad No. Pin Name 75 Y75 76 Y76 77 Y77 78 Y78 79 Y79 80 Y80 81 Y81 82 Y82 83 Y83 84 Y84 85 Y85 86 Y86 87 Y87 88 Y88 89 Y89 90 Y90 91 Y91 92 Y92 93 Y93 94 Y94 95 Y95 96 Y96 97 Y97 98 Y98 99 Y99 100 Y100 101 Y101 102 Y102 103 Y103 104 Y104 105 Y105 106 Y106 107 Y107 108 Y108 109 Y109 110 Y110 111 Y111
TM Technology Inc. reserves the right P. 31 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
X -1726.25 -1786.25 -1846.25 -1906.25 -1966.25 -2026.25 -2086.25 -2146.25 -2206.25 -2266.25 -2326.25 -2386.25 -2446.25 -2506.25 -2566.25 -2626.25 -2686.25 -2746.25 -2806.25 -2866.25 -2926.25 -2986.25 -3046.25 -3106.25 -3166.25 -3226.25 -3286.25 -3346.25 -3406.25 -3466.25 -3526.25 -3586.25 -3646.25 -3706.25 -3766.25 -3826.25 -3886.25 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 Pad No. Pin Name 186 Y186 187 Y187 188 Y188 189 Y189 190 Y190 191 Y191 192 Y192 193 Y193 194 Y194 195 Y195 196 Y196 197 Y197 198 Y198 199 Y199 200 Y200 201 Y201 202 Y202 203 Y203 204 Y204 205 Y205 206 Y206 207 Y207 208 Y208 209 Y209 210 Y210 211 Y211 212 Y212 213 Y213 214 Y214 215 Y215 216 Y216 217 Y217 218 Y218 219 Y219 220 Y220 221 Y221 222 Y222
T66H0001A
X -3946.25 -4006.25 -4066.25 -4126.25 -4186.25 -4246.25 -4306.25 -4366.25 -4426.25 -4486.25 -4546.25 -4606.25 -4666.25 -4726.25 -4786.25 -4846.25 -4906.25 -4966.25 -5026.25 -5086.25 -5146.25 -5206.25 -5266.25 -5326.25 -5386.25 -5446.25 -5506.25 -5566.25 -5626.25 -5686.25 -5746.25 -5806.25 -5866.25 -5926.25 -5986.25 -6046.25 -6106.25 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4
Pad No. Pin Name 149 Y149 150 Y150 151 Y151 152 Y152 153 Y153 154 Y154 155 Y155 156 Y156 157 Y157 158 Y158 159 Y159 160 Y160 161 Y161 162 Y162 163 Y163 164 Y164 165 Y165 166 Y166 167 Y167 168 Y168 169 Y169 170 Y170 171 Y171 172 Y172 173 Y173 174 Y174 175 Y175 176 Y176 177 Y177 178 Y178 179 Y179 180 Y180 181 Y181 182 Y182 183 Y183 184 Y184 185 Y185
TM Technology Inc. reserves the right P. 32 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
TE CH
X -6166.25 -6226.25 -6286.25 -6346.25 -6406.25 -6466.25 -6526.25 -6586.25 -6646.25 -6706.25 -6766.25 -6826.25 -6526.25 -6586.25 -6646.25 -6706.25 -6766.25 -6826.25 -7154.4 -7069.4 -6934 -6849 -6713.6 -6628.6 -6493.2 -6408.2 -5043.05 -4958.05 -4454.3 -4369.3 -4179.95 -4076.45 -3945.05 -3841.55 -3736.45 -3632.95 -3501.55 Y 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 418.4 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 Pad No. Pin Name 260 DI1 261 DI2 262 DI2 263 DI3 264 DI3 265 DI4 266 DI4 267 DI5 268 DI5 269 DI6 270 DI6 271 DI7 272 DI7 273 XCK 274 XCK 275 DISPOFF 276 DISPOFF 277 LP 278 LP 279 EIO1 280 EIO1 281 FR 282 FR 283 LR24 284 LR24 285 MD 286 GND 287 GND 288 V5R 289 V5R 290 V43R 291 V43R 292 V12R 293 V12R 294 V0R 295 V0R
T66H0001A
X -3398.05 -3292.95 -3189.45 -3058.05 -2954.55 2596.4 2699.9 2805 2908.5 3039.9 3143.4 3248.5 3352 3483.4 3586.9 3692 3795.5 3926.9 4030.4 4135.5 4239 4370.4 4473.9 4616.9 4720.4 4880.85 5069.45 5154.45 6408.2 6493.2 6628.6 6713.6 6849 6934 7069.4 7154.4 Y -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454 -454
Pad No. Pin Name 223 Y223 224 Y224 225 Y225 226 Y226 227 Y227 228 Y228 229 Y229 230 Y230 231 Y231 232 Y232 233 Y233 234 Y234 235 Y235 236 Y236 237 Y237 238 Y238 239 Y239 240 Y240 241 V0L 242 V0L 243 V12L 244 V12L 245 V43L 246 V43L 247 V5L 248 V5L 249 GND 250 GND 251 VDD 252 VDD 253 SC 254 SC 255 EIO2 256 EIO2 257 DI0 258 DI0 259 DI1
TM Technology Inc. reserves the right P. 33 to change products or specifications without notice.
Publication Date: JUL. 2002 Revision:A
tm
Pad No.
TE CH
X Y 339.75 449.85 449.85 339.75 -360.4 -449.85 -449.85 -449.85 -449.85 -449.85 -449.85 -360.4
T66H0001A
Pin Name Dummy RT
7370 7291.35 -7291.35 LT -7370 -7370 LB -7274.5 Middle -2355.85 -2137 -1674.8 2356.45 7274.5 RB 7370
Appendix:
TM Technology Inc. reserves the right P. 34 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A

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